1. Field of the Invention
The present invention relates to a high voltage generating circuit and method for using the same, and more particularly, to an improved high voltage generation circuit that generates a high voltage during a programming operation or an erasing operation with regard to a flash memory apparatus, and a method for generating a signal that maintains high voltage and current characteristics therewith.
2. Description of the Background Art
When a flash memory is programmed or erased, a high voltage and a high current need to be applied to memory cell drains in the flash memory. Such a high voltage and a high current are generated through an external voltage. At this time, in order to reduce unnecessary power consumption, the high voltage should be maintained at a constant level. To achieve such a constant voltage, a circuit is required for regularly maintaining an output voltage without regard to an external power source or an output current.
U.S. Pat. No. 5,422,586 discloses a conventional charge pump for generating a high voltage and a high current during an erasing operation or a programming operation in a flash memory array.
As shown in FIG. 1, the charge pump according to the background art includes NMOS transistors NM11-NM14 serially connected between an external source voltage Vcc and an output voltage Vout. A pair of clock signals CLK1, CLK2 are provided from sources SOURCE1 and SOURCE2 through capacitors C24-C26 to the charge pump circuit, and the same pairs of clock signals CLK1, CLK2 are furnished from the sources SOURCE1 and SOURCE2 through capacitors C21-C23 to the charge pump circuit. Also, MOS transistors NM15-NM17 are correspondingly connected to gate terminals of the NMOS transistors NM11-NM13.
The operation of the conventional charge pump circuit will now be described.
First, when the second clock signal CLK2 has a high level, as shown in FIG. 2, the second clock signal CLK2 is applied to the gate terminals of the transistors NM15, NM17, thereby turning on the transistors NM15, NM17. Also, the clock signal CLK2 is applied to the gate terminal of transistor NM12, and a high voltage is applied from the second source SOURCE2 to the drain terminal of the transistor NM12. Since high voltages are applied to the gate and drain of the transistor NM12, the transistor NM12 is turned on. When the transistor NM12 is turned on, its gate and drain are initialized with the same value. However, when the first clock signal CLK1 has a low signal, the transistor NM16 for connecting the gate and drain of the transistor NM12 is turned off. Therefore, when the transistor NM12 is turned on for some time, the high voltage at the drain of the transistor NM12 is transmitted to charge the first capacitor C21 and the second capacitor C22, thereby decreasing the voltage level at the drain of the transistor NM12. This causes the gate voltage to become higher than the drain or the source voltage of the transistor NM12. In order to increase the current for the next stage, the switching is completely done without lowering any threshold voltage drop.
When the voltages at the drain and the source of the transistor NM12 become equal, the gate voltage of the transistor is increased and almost turned on. If the second clock signal CLK2 has a low level, the transistor NM16 is turned on. When the second clock signal CLK2 has a low level, the voltage drop at the gate of the transistor NM12 allows the transistor NM12 to turn off. Also, in response to a low level second clock signal CLK2, the voltages at the gate terminals of the transistors NM15, NM17 are lowered to turn off the transistors NM15, NM17, so that the drains and gates of each of the transistors NM11, NM13 become different from each other. When the first clock signal CLK1 has a high level, the transistor NM16 is completely switched on, causing the voltage level of the gate and drain of the transistor NM12 to equalize. At the same time, when the voltage at the drain of the transistor is increased according to the external source voltage Vcc, the voltages at the gate terminals of the transistors NM11, NM12 are increased by the external source voltage Vcc.
The switching transistors NM11, NM13 are driven in a manner similar to the switching transistor NM12 in transmitting a charge to the capacitors C21, C23. The gates and drains of such transistors have same voltages in initial stages, however, the drain voltage is dropped as much as the voltage transmitted to the capacitors C21, C23 in the subsequent stage so that the transistors are completely turned on without dropping a threshold voltage thereof.
Therefore, when the clock signal CLK1 has a high level, the switching transistor NM11 is turned on and the current supplied by the external source voltage Vcc is used to charge capacitor C21. By contrast, when the first clock signal CLK1 has a low level, the switching transistor NM11 is turned off. Then, when the second clock signal CLK2 has a high level, the switching transistor NM12 is turned on and the capacitor C21 is supplied with a charge to be stored from the second clock signal CLK2 which serves to charge the capacitor C22. When the second clock signal CLK2 has a low level, the switching transistor NM12 is switched off, and when the first clock signal CLK1 is again turned to a high level, the external source voltage Vcc also serves to charge the capacitor C21. Subsequently, the switching transistor NM13 is turned on, and the capacitor C22 applies the pulse from the first clock signal CLK1 as well as the stored charge to the capacitor C23. When the first clock signal CLK 1 has a low level, the switching transistor NM13 is turned off. When the second clock signal CLK2 is later turned to a high level, the output transistor NM14 is turned on to supply a pumped voltage at Vout, which pumped voltage has a level approximately equal to the number of stages plus one multiplied by the value of source voltage Vcc less the threshold voltage drop of the output transistor NM14.
As a result, the charging of the capacitor C23 and the positive swing of the second clock signal CLK2 raise the voltage level on the capacitor C23 sufficiently above the level of output voltage Vout to cause the conduction of the switching transistor NM14. This provides the desired output voltage while furnishing the high level of current necessary to erase and program flash EEPROM memory arrays.
According to the background art, when the second clock signal CLK2 has a high level, the gate and drain of the transistor NM12 become identical in electrical potential, and the charge pumped in the capacitor C21 begins to be transferred to the capacitor C22. Also, as the charge begins its transmission, the potential at the drain of the NMOS transistor NM12 becomes higher than that of its gate, whereby all the potential is transferred without the threshold voltage drop. However, when the precharged potential has been completely transferred to the output terminal, power consumption is unnecessarily experienced since the threshold voltage of the NMOS transistor NM14 is dropped. Also, since the background art employs the transmission transistor NM12 (e.g., an S-type transistor of about 0.3V) having a low threshold voltage, there occurs a voltage difference between the drain and the source of the transmission transistor NM12, whereby the voltage level of the output signal Vout becomes lower than the desired voltage level.
Further, the background art has a disadvantage in that the external voltage is not available to other devices (e.g., a 5V of source voltage Vcc) when the external source voltage is set to a different constant voltage level (e.g., a 3V of source voltage Vcc).